module sliver_write(
	input				clk_in,     	//100M
	input				rst_n,
	output	reg			SPI_SDO,
	input				CS,
	input				SPI_SCLK,
	input				SPI_SDI,
	output	reg [7:0]	rdA_CH,
	output	reg [7:0]	rdB_CH,

	output	reg	[15:0]	CMD,     	//地址
	input		[31:0]	DATA1,   	//待传输数据
	input		[31:0]	DATA2,   	//待传输数据
	output	reg			send_flog	//发送标志
);

//*************************送入FPGA的各种数据或者信号，属于不同时钟域的，故需要做同步
reg spi_cs_0,spi_cs_1;  /* 延时两个时钟，配合检测时钟边沿 */
reg spi_sck_0,spi_sck_1;
reg spi_mosi_0,spi_mosi_1;
wire spi_cs_neg;
wire spi_sck_pos;  //时钟上升沿读取数据
wire spi_sck_neg; //时钟下降沿读取数据
//wire spi_cs_flag;
wire spi_miso_flag;

always @(posedge clk_in or negedge rst_n) begin
	if (!rst_n) begin
		{spi_cs_1,spi_cs_0}		<= 2'b11;
		{spi_sck_1,spi_sck_0}	<= 2'b00;
		{spi_mosi_1,spi_mosi_0}	<= 2'b00;
	end else begin
		{spi_cs_1,spi_cs_0}		<= {spi_cs_0,CS};
		{spi_sck_1,spi_sck_0}	<= {spi_sck_0,SPI_SCLK};
		{spi_mosi_1,spi_mosi_0}	<= {spi_mosi_0,SPI_SDI};
	end
end

assign spi_miso_flag	= spi_mosi_1; //同步后的MISO数据
assign spi_sck_pos		= (!spi_sck_1	) && (spi_sck_0		);  /* 取上升沿 */
assign spi_sck_neg		= (spi_sck_1	) && (!spi_sck_0	);  /* 取下降沿 */
assign spi_cs_neg		= (spi_cs_1		) && (!spi_cs_0		);    /* 取spi_cs下降沿，作为开始信号 */


localparam	READY		= 4'd1;
localparam	data_CMD	= 4'd2;
localparam	data_DATA	= 4'd3;
localparam	data_RD		= 4'd4;
localparam	OVER		= 4'd5;

reg[3:0] state;
reg[7:0] cnt_CMD;
reg[7:0] cnt_data1;
reg[7:0] cnt_data2;
reg[15:0] CMD1;

always @(posedge clk_in or negedge rst_n) begin
	if (!rst_n) begin
		state		<= READY;
		cnt_CMD		<= 8'd15;
		cnt_data1	<= 8'd33;
		cnt_data2	<= 8'd33;
		CMD1		<= 16'h0;
		SPI_SDO		<= 1'b0;
		send_flog	<= 1'b0;
	end else begin
		case (state)
			READY: begin
				if (spi_cs_neg) begin
					state		<= data_CMD;
					cnt_CMD		<= 8'd15;
					cnt_data1	<= 8'd33;
					cnt_data2	<= 8'd33;
					CMD1		<= 16'h0;
					CMD			<= 16'h0;
					SPI_SDO		<= 1'b0;
					send_flog	<= 1'b0;
					rdA_CH		<= 8'h0;
					rdB_CH		<= 8'h0;
				end else begin
					state		<= READY;
				end
			end
			data_CMD: begin
				if (spi_sck_neg) begin
					if (cnt_CMD > 8'd0) begin
						CMD1[cnt_CMD]	<= spi_miso_flag;
						cnt_CMD			<= cnt_CMD - 8'd1;
						SPI_SDO			<= 1'b0;
					end else begin
						CMD1[0]			<= spi_miso_flag;
						state			<= data_DATA;
						SPI_SDO			<= 1'b0;
					end
				end else begin
					state		<= data_CMD;
					SPI_SDO		<= 1'b0;
				end
			end
			data_DATA: begin
				if (spi_sck_pos) begin
					if (cnt_data1 > 8'd0) begin
						SPI_SDO		<= DATA1[cnt_data1 - 1'b1];
						cnt_data1	<= cnt_data1 - 1'd1;
						CMD			<= CMD1;
					end else begin
						SPI_SDO		<= DATA1[0];
						state		<= data_RD;
					end
				end else begin
					state		<= data_DATA;
					SPI_SDO		<= SPI_SDO;
				end
			end
			data_RD: begin
				case (CMD1)
					16'h0101: begin
						rdA_CH	<= 8'd1;
						state	<= OVER;
					end
					16'h0102: begin
						rdA_CH	<= 8'd2;
						state	<= OVER;
					end
					16'h0103: begin
						rdA_CH	<= 8'd4;
						state	<= OVER;
					end
					16'h0104: begin
						rdA_CH	<= 8'd8;
						state	<= OVER;
					end
					16'h0105: begin
						rdA_CH	<= 8'd16;
						state	<= OVER;
					end
					16'h0106: begin
						rdA_CH	<= 8'd32;
						state	<= OVER;
					end
					16'h0107: begin
						rdA_CH	<= 8'd64;
						state	<= OVER;
					end
					16'h0108: begin
						rdA_CH	<= 8'd128;
						state	<= OVER;
					end
					16'h0201: begin
						rdB_CH	<= 8'd1;
						state	<= OVER;
					end
					16'h0202: begin
						rdB_CH	<= 8'd2;
						state	<= OVER;
					end
					16'h0203: begin
						rdB_CH	<= 8'd4;
						state	<= OVER;
					end
					16'h0204: begin
						rdB_CH	<= 8'd8;
						state	<= OVER;
					end
					16'h0205: begin
						rdB_CH	<= 8'd16;
						state	<= OVER;
					end
					16'h0206: begin
						rdB_CH	<= 8'd32;
						state	<= OVER;
					end
					16'h0207: begin
						rdB_CH	<= 8'd64;
						state	<= OVER;
					end
					16'h0208: begin
						rdB_CH	<= 8'd128;
						state	<= OVER;
					end
					default: begin
						rdA_CH	<= 8'h0;
						rdB_CH	<= 8'h0;
						state	<= OVER;
					end
				endcase
			end
			OVER: begin
				SPI_SDO		<= 1'b0;
				send_flog	<= 1'b1;
				state		<= READY;
				rdA_CH		<= 8'h0;
				rdB_CH		<= 8'h0;
			end
			default: begin
				state		<= READY;
				SPI_SDO		<= 1'b0;
			end
		endcase
	end
end



endmodule


